The escalating requirements for density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require planarized layers with minimal spacing between conductive wiring lines.
A traditional method for forming interconnection structures comprises forming a through-hole to expose underlying conductive material of a conductive wiring pattern on a lower level of a semiconductor device, wherein the wiring pattern serves as a landing pad occupying the entire bottom surface portion of the through-hole. Upon filling the through-hole with conductive material to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the conductive pattern. Such a conventional technique is illustrated in FIGS. 1A and 1B, wherein conductive pattern 10 formed on first insulating layer 15 is exposed by through-hole 12 formed in second insulating layer 11. In accordance with conventional practices, through-hole 12 is formed in such a way that conductive pattern 10 occupies its entire bottom surface and encloses it thereby serving as a landing pad for conductive material 13 which fills the through-hole 12 to form conductive via 16 electrically connecting upper conductive wiring pattern 10a to lower conductive wiring pattern 10. As shown in FIGS. 1A and 1B, lower conductive wiring pattern 10 extends beyond the bottom contact surface by a distance 14. Thus, the entire bottom surface of conductive via 16 is in direct contact with conductive pattern 10.
A problem attendant upon such a conventional landing pad practice of completely enclosing the bottom surface of the conductive via with the conductive pattern is use of a significant amount of precious real estate on a semiconductor chip with conductive material, which is antithetic to escalating high densification requirements.